1. Field of the Invention
This invention relates to interfacing various subsystems of a computer system, and more particularly to memory buses which accommodate burst mode data transfers.
2. Description of the Relevant Art
Modern backplane buses typically support bursting where a single address phase is followed by a sequence of data phases. Because only the first address is provided by the bus master and multiple data words are transferred based on that single address, the bandwidth of bursted bus transfers is greater than single-word, explicitly addressed transfers. Two typical uses of burst mode transfers are cache line fills from memory and Direct Memory Access (DMA).
Implicit in any burst scheme is an address order for transfers of subsequent data. Coordinated data transfers are accomplished by prior agreement as to the burst order. All senders and all receivers of burst data must agree on this order. Typically, the burst order is determined by the requirements of the processor.
The most common order is sequential based on memory address. However, other orders are possible. For example, the widely used i486 microprocessor and the recently introduced PENTIUM microprocessor, both available from INTEL Corporation of Santa Clara, Calif., have architectures which use a burst order that varies depending on the address of the first data word accessed. Table 1 summarizes these burst order sequences, which are known as the i486 microprocessing burst order sequences. These sequences allow interleaved, DRAM-based memory systems to efficiently mask row and column address setup times for subsequent accesses, thereby maximizing data transfer bandwidth.
TABLE 1 ______________________________________ Access Begins With: First Second Third Fourth Word Word Word Word ______________________________________ BURST 0 1 2 3 ORDER 1 0 3 2 (Word) 2 3 0 1 3 2 1 0 ______________________________________
Memory bus systems in which the burst order is established by prior agreement impose a performance disadvantage when used with certain bus masters such as direct memory access, or DMA, controllers, which naturally prefer a sequential burst order regardless of the first data word accessed. To exploit burst transfers from memory to the CPU (e.g., for cache line fills), a design which implements burst order sequences such as the i486 microprocessor burst sequences is required. Unfortunately, this limits the ability of certain other subsystems to exploit burst transfers. These other systems, which include DMA controllers and other processors or co-processors, require burst data in sequential address order.
The problem is best illustrated by a computer system which includes, for example, a Pentium microprocessor, a memory bus, an interleaved memory subsystem designed to support i486 microprocessor burst sequences, and a DMA controller. Because the i486 microprocessor burst order is a function of the initial data transfer address (see Table 1), the system burst order coincides with that desired by the DMA controller (i.e., sequential) only when the initial address is 4-word aligned (i.e., when the low order bits are 00). When, for example, the DMA controller initiates a transfer where the initial address is not 4-word aligned (i.e., when the low order bits are 01, 10, or 11), the transfer must be broken into separate transactions.
If the initial address of a data transfer from memory to a DMA device is not 4-word aligned (e.g., when the initial address is at address x01) data presented using the non-sequential addressing scheme of i486 microprocessor burst order is incompatible with the sequential burst order required by the DMA controller. One approach to avoiding this problem is to require the DMA controller to request data in multiple transactions. Unfortunately, this approach forgoes much of the bandwidth offered by burst mode, implicitly addressed transfers. First, the controller must explicitly request data at x01. Next, the controller must request either a short burst (x10 and x11) or two explicitly addressed transfers. Finally, the remainder of the data can be transferred in burst mode as it is 4-word aligned.
For large blocks of contiguous data this inefficiency could be amortized across many data words. However, for smaller blocks, data transfer bandwidth typically is significantly impaired. In addition to the bandwidth impairment, a system which supports only non-sequential burst order requires implementation of additional logic within the DMA subsystem to ensure compatibility. This requirement limits the opportunity for use of low-cost, existing DMA controllers which rely on sequential burst ordering.
Although the problem is best described in the context of the specific incompatibility between the i486 and Pentium type microprocessors and DMA controller burst orders, it is in fact generic to any conflict between burst order requirements of bus masters. Such a conflict might arise between two processors which require different burst ordering, between a processor and a DMA controller, between a processor and a LAN controller, etc. Current memory bus systems require that performance of one subsystem be sacrificed because only a single burst order is supported.